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Deep-level transient spectroscopy (DLTS) is an experimental tool for studying electrically active defects (known as charge carrier traps) in semiconductors. DLTS establishes fundamental defect parameters and measures their concentration in the material. Some of the parameters are considered as defect "finger prints" used for their identifications and analysis.
DLTS investigates defects present in a space charge (depletion) region of a simple electronic device. The most commonly used are Schottky diodes or p-n junctions. In the measurement process the steady-state diode reverse is disturbed by a voltage pulse. This voltage pulse reduces the electric field in the space charge region and allows free carriers from the semiconductor bulk to penetrate this region and recharge the defects causing their non-equilibrium charge state. After the pulse, when the voltage returns to its steady-state value, the defects start to emit trapped carriers due to the thermal emission process. The technique observes the device space charge region capacitance where the defect charge state recovery causes the capacitance transient. The voltage pulse followed by the defect charge state recovery are cycled allowing an application of different signal processing methods for defect recharging process analysis.
The DLTS technique has a higher sensitivity than almost any other semiconductor diagnostic technique. For example, in silicon it can detect impurities and defects at a concentration of one part in 1012 of the material host atoms. This feature together with a technical simplicity of its design made it very popular in research labs and semiconductor material production factories.
In conventional DLTS the capacitance transients are investigated by using a lock-in amplifier or double box-car averaging technique when the sample temperature is slowly varied (usually in a range from liquid nitrogen temperature to room temperature 300 K or above). The equipment reference frequency is the voltage pulse repetition rate. In the conventional DLTS method this frequency multiplied by some constant (depending on the hardware used) is called the "rate window". During the temperature scan, peaks appear when the emission rate of carriers from some defect equals the rate window. By setting up different rate windows in subsequent DLTS spectra measurements one obtains different temperatures at which some particular peak appears. Having a set of the emission rate and corresponding temperature pairs one can make an Arrhenius plot, which allows for the deduction of defect activation energy for the thermal emission process. Usually this energy (sometimes called the defect energy level) together with the plot intercept value are defect parameters used for its identification or analysis. On samples with low free carrier density conductance transients have also been used for a DLTS analysis.
In addition to the conventional temperature scan DLTS, in which the temperature is swept while pulsing the device at a constant frequency, the temperature can be kept constant and sweep the pulsing frequency. This technique is called the frequency scan DLTS. In theory the frequency and temperature scan DLTS should yield same results. Frequency scan DLTS is specifically useful when an aggressive change in temperature might damage the device. An example when frequency scan is shown to be useful is for studying modern MOS devices with thin and sensitive gate oxides.
MCTS and minority-carrier DLTS
For Schottky diodes, majority carrier traps are observed by the application of a reverse bias pulse, while minority carrier traps can be observed when the reverse bias voltage pulses are replaced with light pulses with the photon energy from the above semiconductor bandgap spectral range. This method is called Minority Carrier Transient Spectroscopy (MCTS). The minority carrier traps can be also observed for the p-n junctions by application of forward bias pulses, which inject minority carriers into the space charge region. In DLTS plots the minority carrier spectra usually are depicted with an opposite sign of amplitude in respect to the majority carrier trap spectra.
There is an extension to DLTS known as a high resolution Laplace transform DLTS (LDLTS). Laplace DLTS is an isothermal technique in which the capacitance transients are digitized and averaged at a fixed temperature. Then the defect emission rates are obtained with a use of numerical methods being equivalent to the inverse Laplace transformation. The obtained emission rates are presented as a spectral plot. The main advantage of Laplace DLTS in comparison to conventional DLTS is the substantial increase in energy resolution understood here as an ability to distinguish very similar signals.
Laplace DLTS in combination with uniaxial stress results in a splitting of the defect energy level. Assuming a random distribution of defects in non-equivalent orientations, the number of split lines and their intensity ratios reflect the symmetry class of the given defect.
Application of LDLTS to MOS capacitors needs device in a range where the Fermi level extrapolated from semiconductor to the semiconductor-oxide interface intersects this interface within the semiconductor bandgap range. The electronic interface states present at this interface can trap carriers similarly to defects described above. If their occupancy with electrons or holes is disturbed by a small voltage pulse then the device capacitance recovers after the pulse to its initial value as the interface states start to emit carriers. This recovery process can be analyzed with the LDLTS method for different device polarization voltages. Such a procedure allows to obtain the energy state distribution of the interface electronic states at the semiconductor-oxide (or dielectric) interfaces.
In general, the analysis of the capacitance transients in the DLTS measurements assumes that the concentration of investigated traps is much smaller than the material doping concentration. In cases when this assumption is not fulfilled then the constant capacitance DLTS (CCDLTS) method is used for more accurate determination of the trap concentration. When the defects recharge and their concentration is high then the width of the device space region varies making the analysis of the capacitance transient inaccurate. The additional electronic circuitry maintaining the total device capacitance constant by varying the device bias voltage helps to keep the depletion region width constant. As a result, the varying device voltage reflects the defect recharge process. An analysis of the CCDLTS system using feedback theory was provided by Lau and Lam in 1982.
I-DLTS and PITS
There is an important shortcoming for DLTS: it cannot be used for insulating materials. (Note: an insulator can be considered as a very large bandgap semiconductor.) For insulating materials it is difficult or impossible to produce a device having a space region for which width could be changed by the external voltage bias and thus the capacitance measurement-based DLTS methods cannot be applied for the defect analysis. Basing on experiences of the thermally stimulated current (TSC) spectroscopy, the current transients are analyzed with the DLTS methods (I-DLTS), where the light pulses are used for the defect occupancy disturbance. This method in the literature is sometimes called the Photoinduced Transient Spectroscopy (PITS). I-DLTS or PITS are also used for studying defects in the i-region of a p-i-n diode.
- Carrier generation and recombination
- Effective mass
- Schottky diode
- Frenkel defect
- Schottky defect
- Semiconductor device
- Vacancy (chemistry)
- Capacitance voltage profiling
- High-k dielectric
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- Laplace transform Deep Level Transient Spectroscopy
- Point Group Symmetry
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