AccelChip DSP Design Automation Tools Facilitate Radar Development at NASA’s Jet Propulsion Laboratory
AccelChip Inc., the industry’s only provider of automated flows from MATLAB(R) algorithms to silicon, today announced that the Jet Propulsion Laboratory (JPL) has selected AccelChip(R) DSP Synthesis and AccelWare(R) IP libraries to develop a digital filter for space-based radar applications. AccelChip’s DSP design automation tools will be used to shorten the design cycle and explore design alternatives, including performance and resource utilization, to obtain the level of optimality required in sensitive radar applications.
JPL will be using the MATLAB language to model the digital filter. The AccelChip algorithmic synthesis tool will then be used to automatically generate synthesizable, bit-accurate VHDL and Verilog from the MATLAB model and provide a testbench for implementation and verification, accelerating the design process.
AccelChip DSP Synthesis and AccelWare IP provide a unified design environment in which high-performance DSP designs are achieved through a highly productive, integrated flow. The toolset also integrates with JPL’s existing CoWare SPW system-level verification tool and their existing FPGA and ASIC flows for greater design efficiency overall.
“JPL needed a solid design methodology similar to what they were already using to generate an on-board, range compression FPGA. AccelChip’s products fit directly into their current design flow and allowed them to explore their design architecture to ensure they had the exacting specifications their application required,” said Tom Feist, vice president of Marketing, AccelChip. “AccelChip was able to return JPL’s design benchmark in just hours, showing them multiple implementation possibilities for their design. By using AccelChip, JPL will now be able to use MATLAB as the golden source for both modeling and implementation, enabling them to apply late design changes easily and flexibly and avoid long and costly redesign work.”
Managed for NASA by the California Institute of Technology, JPL has exciting missions spread throughout the solar system. It handles such projects as the 2004 Mars rover landings, the Cassini spacecraft, which is currently undergoing a four-year study of Saturn, and the Deep Space Network, an international network of antennas that support communications between distant spacecraft and Earth-based teams. JPL missions also turn a watchful eye on the Earth, using spacecraft and instruments aboard NASA satellites to expand knowledge of our home planet. Technologies developed for space often have other applications in fields such as medical, communications, security, and more.
About AccelChip
AccelChip Inc. develops and markets a MATLAB-based algorithmic synthesis environment and intellectual property that automate the development and implementation of DSP designs. The company’s unique DSP Design Automation (DDA) solutions reduce design iterations, accelerate the creation and verification of register-transfer language (RTL), and link the domain-specific DSP design environment with industry-standard hardware design flows targeting FPGAs and ASICs. Founded in 2000, AccelChip is located in Milpitas, California, and has design centers in Portland, Oregon, and Carlsbad, California. AccelChip’s Web address is www.accelchip.com .
AccelChip and AccelWare are registered trademarks of AccelChip Inc. All other trade names referenced are the service marks, trademarks, or registered trademarks of their respective companies.
